Vol. 59 n°7-8, July-August 2004
Systems on chip for telecommunications
Guest editors: Jean-François Naviner* and Amara Amara**
Foreword : Systems-on-chip for telecommunications
Jean-François NAVINER*, Amara AMARA**
GET/Télécom Paris, UMR CNRS 5141, 46 rue Barrault - 75634 Paris cedex 13 France
**ISEP Institut Supérieur d'Electronique de Paris - 28, rue Notre Dame des Champs - 75006 Paris
A system-on-chip (abbreviated: SoC) consists of the integration in a unique package of all electronic parts of a "system", on a single integrated circuit, also called chip or microchip. Here, the concept of system covers every kind of signal acquisition or restitution, signal processing and/or computing material unit designed to respond to a particular use like a digital camera, a smartphone, some biomedical implants... The definition actually covers a great variety of different technologies, architectures, constraints and complexity. Whatever the targeted system, the main pursued objective through a SoC implementation is to obtain high performance at low cost. Again, the desired performance may cover different system characteristics like volume or surface, reliability, energy consumption, computation power, security, etc. [...]
Evolution of SoC technology and architectures for telecom applications
Hervé FANET*, Jean-René LEQUEPEYS*
* CEA-Léti ; CEA Grenoble, 17, rue des Martyrs, 38054 Grenoble Cedex 9, France.
Abstract: Market demand in the telecom area is leading to the design of increasingly complex chips. This paper tries to indicate the most significant trends: evolution of CMOS technology, contribution of nanotechnologies and evolution of architectures.
Key words: Semiconductor chip, System on chip, Semiconductor technology, System architecture, Telecommunication application, Technical progress, Integrated system, Complementary MOS technology, Nanostructure, Microstructure.
A generic architecture model based methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Nacer-Eddine ZERGAINOH*, Amer BAGHDADI**, Ahmed Amine JERRAYA*
* TIMA Laboratory, National Polytechnique Institute of Grenoble, 46, avenue Felix Viallet 38031 Grenoble Cedex France
** GET/ENST Bretagne, Electronic Engineering Department, CS 83818, 29285 Brest cedex, France
Abstract: In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip (MP-SoC). Our approach is based on a generic architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level (RTL) consists of two principal stages. The first stage is architecture exploration where the system-level performance estimation method is required to find the best system architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce the RTL architecture. This paper focuses on the definition of the architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
Key words: System on chip, System architecture, Multiprocessor, System design, Methodology, Telecommunication application, Switch, Network routing, Mobile station, CDMA, Modem, VDSL.
Integration of parallel «C» specifications on hardware/software platforms
Ivan AUGÉ*, Frédéric PÉTROT*, François DONNET*, Pascal GOMEZ*
* Département ASIM du Laboratoire d'Informatique de Paris VI Université Pierre et Marie Curie Paris, France. UPMC LIP6 ASIM CNRS, 4, place Jussieu 75252 Paris cedex 05 France
Abstract: This paper presents DISYDENT, a framework dedicated to System on a Chip (SoC) platform design. A platform based design problem is a triplet (system, new application, constraints) where system is both an operating system and a hardware template that can be enhanced with dedicated co-processors. Our contribution is firstly the definition of a complete flow for platform based design, from application to integration including all necessary intermediate steps, and secondly a set of tightly bound, operational, tools to implement the flow DISYDENT is based on 4 tools. DPN is a ‘C' library for describing Kahn Process Network, CASS is a cycle accurate simulator, ASIM0 is a multiprocessor target platform running a micro-kernel. The platform can be enhanced with co-processors. UGH is a high level synthesis tool. DISYDENT proposes a design flow to quickly focus on a solution for a platform based design problem. To start with, the designer models the new application in ‘C' as a Kahn Process Network using the DPN library, The functional validation is performed by running the application on the host. Temporal profiling at cycle accurate level is obtained by simulating the platform running the application with the CASS tool. Then, based on the profiling, the designer selects a group of processes to migrate from software to hardware. To make sure that the selection is promising, DISYDENT proposes the exploratory migration feature. It consists in enhancing the initial platform with coprocessors realizing the selected processes without modification of their description. The simulation of the enhanced platform running the application with the CASS tool gives the temporal informations that allows to accept or reject the group. Finally, the selected processes are synthesized with UGH. For each process, in addition to a RTL synthesizable description, UGH also provides a cycle accurate model. A last CASS simulation of the platform enhanced with these new models allows to perform the final validation. DISYDENT strength relies on its formal Kahn Process Network model that ensures a behavior that is independent of the overall system scheduling and its fast cycle accurate validation that is several order of magnitude faster than classical event driven simulators.
Keywords : System on chip, System design, C language, Programming environment, Integrated system, Hardware, Software, Simulation, Telecommunication application, Decoder, JPEG, Moving image.
Development process of a DRM digital broadcast SoC receiver platform
Jérôme QUÉVREMONT*, Michel SARLOTTE*, Bernard CANDAELE*
* THALES Communications - 160, boulevard de Valmy - BP 82 - 92704 Colombes Cedex - France
Abstract: The new DRM standard for digital radio broadcast in the AM band requires integrated devices for radio receivers at low cost and very low power. A chipset has been developed based on an ARM9 dual-core architecture. This paper introduces the application itself, and then presents the development process followed to design such a chip covering the hardware/ software partitioning, the architecture definition and all the validation issues. The RF part that partially drives the baseband is also briefly presented. The legal aspects are also investigated. Then as a conclusion, this paper presents the next steps of this development and the methodological gap in the system on chip design process.
Key words: Sound broadcasting, Digital broadcasting, System on chip, Sound broadcasting receiver, System design, Kilometric wave, Hectometric wave, Decametric wave, Integrated system, Consumer electronics, System architecture, Intellectual property.
Radio-frequency SoC topologies: some solutions for low consumption
Sylvain BOURDEL*, Philippe PANNIER*, Hervé BARTHÉLÉMY*, Nicolas DEHAESE*
* L2MP UMR CNRS 6137 Polytech'Marseille, IMT Technopôle de Château Gombert, 13451 Marseille Cedex 20, France
Abstract: This paper is a discussion on 2.45 GHz RF SoC for low cost applications. Starting from cost considerations, design of analogue, digital and mixed parts is discussed. In this context, some topologies and some technological choices are proposed. The possible use of the presented solutions in the 802.15.4 standard is also analysed. Thus, using a comparative analysis, this paper shows the interest of a Zero-IF direct conversion associated with FSK modulation. The communication protocol impact on the design is also discussed. Many topology drawbacks are also highlighted for Low-cost RF SoC.
Key words: Transceiver, System on chip, Energy consumption, System architecture, Integrated system, Consumer electronics,Wireless LAN, Frequency conversion, Low rate, Modulation, Cost, Low energy.
Power Consumption Reduction in Systems on Chips (SoCs)
* CSEM and LAP-EPFL ; CSEM, Jaquet-Drotz 1, 2000 Neuchâtel, Suisse.
Abstract: Systems on Chips are becoming extremely complex integrated circuits, containing tens or hundreds of analog, RF and digital blocks. For most applications, they have to present extremely low power consumption. It is the case, for instance, in ad hoc networks for which 100 or 1000 SoC nodes have to sense their environment, do some processing and send by radio some information to adjacent nodes in a multi-hop fashion to reach finally a base station. The design of such SoC nodes, to achieve the required extremely low power consumption, has to performed first at the system level, including low power communication protocols and data routing through the network, node wake-up strategies, low-power software and operating systems, innovative solutions for the sensor part, flexible or reconfigurable and very low power digital processing, low-power networks on chip for the communication between embedded processors and memories, as well as low power RF front-ends. In addition, due to the impressive technology pace, new problems have to be solved for the design of SoCs, such as the interconnect delays, reliability and the dramatic increase of the static power. Some techniques, considered as the most efficient, of dynamic as well as static power reduction are described. It is however shown that the design of SoCs in 130 nm and below will impact dramatically the design methodologies, mainly due the static power increase. Finally, if today most SoCs are powered by batteries, alternative sources of energy are reviewed.
Key words: System on chip, Energy consumption, Electric power, Mobile radiocommunication, Ad hoc network, Low energy, Electric source.
Overview of power/energy consumption analysis and optimization tools in SoCs
* Laboratoire des Systèmes Temps Réels (LESTER), Université de Bretagne Sud-Lorient, Centre de Recherche, rue de Saint Maudé B.P. 92116, 56321 Lorient Cedex, France
Abstract: Power and energy consumption is currently a critical problem in digital signal and image processing applications; the emergence of System-on-Chip (SoCs) makes the power analysis difficult by increasing the system heterogeneity, density and performances. To take into account this problem and efficiently focus the actions, we will first examine the main sources of the power consumption and its distribution in circuits and systems; then we will propose a non exhaustive overview of estimation and optimization methods and available tools together with the needs and perspectives in low power SoC design.
Key words: System on chip, Energy consumption, Electric power, Low energy, Energy management, Integrated system, Hardware, Software, Optimization, Memory.
Monolithic Distributed Power Management for System-on-a-Chip (SoC)
Siamak ABEDINPOUR*, Bertan BAKKALOGLU**, Sayfe KIAEI***
* Semiconductor Products Sector, Motorola, Tempe, AZ.
** Texas Instruments, Dallas, Texas.
***Connection One Research Center, Arizona State University, Tempe, AZ.
Abstract: With increasing drive towards higher level of integration, lower cost, and longer battery life in wireless applications, there is a need for efficient monolithic DC-DC power converters. This tutorial paper summarizes the topology tradeoffs that are involved in the implementation of monolithic distributed power management in the future generations of SoCs for portable wireless applications. These circuits have a broad range of requirements including high power density, high energy efficiency, low noise, small size, and low cost. The advantages and disadvantages of each of the competing topologies, namely low-dropout linear, switchedcapacitor, and switched-mode DC-DC converters are examined in light of these requirements.
Key words: System on chip, Energy management, Direct current converter, Monolithic integrated circuit, Distributed system, Portable telephone set, Mobile station, Linear circuit, Voltage regulation, Switched capacitor, Switched mode, Technology.
Power and battery management IC's for low-cost portable Electronics
Hafid AMRANI*, Hubert CORDONNIER*
* ATMEL, Zone Industrielle, 13106 Rousset Cedex, France ; Email: email@example.com
Abstract: Handheld devices such as mobile phones have exacting power management. Different elements require special supply voltage and have also different requirement in terms of noise, power supply rejection ratio (PSRR) etc. Power management ICs consist mainly of voltage and currents regulators. Linear and switched regulators are implemented in every portable Devices, cellular phones, pagers, laptops, etc. to provide good regulated power supplies of each part in a complex circuit. Low quiescent current of high performance linear regulators and high efficiency of pulse-width-modulation DCDC converters are the most important parameters for the battery autonomy. Battery chargers interface is very important function in the battery management integrated circuit, which allows the control of the charge of the battery with the maximum battery autonomy without reducing its life. This paper discuses and presents some techniques and new architectures that enable the practical realizations of full chip combining the power and the battery management with high performance. These high performance full chips are achieved using a classical CMOS technology.
Key words: Integrated circuit, Portable equipment, Energy management, Electric power, Electric source, Consumer electronics, Complementary MOS technology, Voltage regulation, Direct current converter, Electrochemical storage battery, Energy consumption.
Asynchronous technology for energy reduction in embedded systems
Laurent FESQUET*, Mohammed ES SALHIENE*, Marc RENAUDIN*
* Laboratoire TIMA, groupe CIS, 46 Avenue Félix Viallet, 38031 Grenoble, France
Abstract: This article presents the benefits of asynchronous systems versus synchronous systems in term of energy reduction in the context of embedded systems and in particular for telecom equipments such as mobile communicating objects. The electrical consumption reduction is obtained at the hardware and software levels. The shutdown technique and the dynamic voltage scaling for asynchronous systems are studied and compared to synchronous systems. Finally, a power management policy is proposed for asynchronous microprocessors processing periodic and sporadic tasks.
Key words: Energy consumption, Electric power, Autonomous system, Operating system, Adaptive system, Asynchronous circuit, Synchronous circuit, Comparative study.
SoC security: a war against side-channels
Sylvain GUILLEY*, Renaud PACALET**
* GET/Télécom Paris, CNRS LTCI (UMR S141), 46 rue Barrault. 75634 Paris Cedex 13, France
** Institut Eurecom BP 193, 2229 route des Crêtes, 06904 Sophia-Antipolis Cedex, France
Abstract: This article presents the state-of-the-art of the physical security of smart devices. Electronic devices are getting ubiquitous and autonomous: their security is thus becoming a predominant feature. Attacks targeting the physical layer are all the more serious as hardware is not naturally protected against them. The attacks typically consist in either tempering with the device so as to make it malfunction or in spying at some information it leaks. Those attacks, either active or passive, belong to the side-channel attack class. Active attacks operate by writing on an ad hoc side-channel: a degree a freedom normally not available to the end-user is modified by force. Passive attacks consist in listening to a side-channel: the attacker is thus able to gain more information about the device operation than it is supposed to. Counter-measures against both types of attacks have been proposed and we show that only some of them are relevant. Active attacks are forfeited by an appropriate detection mechanism and passive attacks by the removal of all sorts of information leakage. As a consequence, securing hardware consists in watching side-channels or removing them if possible. The increase of security is mainly driven by two trends: integration of the system (on a SoC) for improved discretion and development of a dedicated symptom-free electronic CAD. SoC security is thus foreseen to become a discipline in itself.